Huawei has unveiled a novel semiconductor design methodology that bypasses the need for extreme ultraviolet (EUV) lithography, targeting a 1.4nm equivalent transistor density by 2031. Announced by He Tingbo, the head of Huawei’s semiconductor division, at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai, the so-called “Tau (τ) Scaling Law” redefines the fundamental metric of chip advancement. Rather than focusing on the geometric shrinking of transistors — the dominant paradigm under Moore’s Law for half a century — Huawei’s approach centres on the time it takes for signals to travel across a chip. This conceptual shift, backed by six years of real-world chip production, positions the company on a trajectory that closes the gap with industry leader TSMC to just three years, despite being cut off from EUV tool access due to US sanctions. The introduction of a proprietary architecture called LogicFolding serves as the technical backbone for this new scaling philosophy, promising dramatic gains in density, power efficiency, and clock speed on existing manufacturing equipment.
The Tau (τ) Scaling Law: A New Axis for Semiconductor Progress
He Tingbo’s presentation at ISCAS 2026 proposed that the semiconductor industry should adopt signal propagation delay — denoted as τ (tau) — as the primary scaling axis. For decades, Moore’s Law drove progress through the physical miniaturisation of transistors, packing ever more switches into the same area. However, as lithography approaches atomic limits and the cost of advanced nodes skyrockets, this geometric approach is losing steam. Huawei argues that instead of asking how small a transistor can be made, engineers should ask how quickly a signal can traverse the chip. This is not merely a theoretical exercise. Huawei disclosed that over the past six years, it has designed and mass-produced 381 chip varieties based on the τ Scaling Law, spanning smartphones, AI computing, and other domains. The company has systematically optimised delay across four layers of the stack — device, circuit, chip, and system — creating a multi-level co-optimisation framework that compensates for the lack of cutting-edge lithography.
LogicFolding: The Core Architecture Behind the Density Leap
Vertical Folding Breaks the Planar Paradigm
Traditional chip designs place digital logic, analogue circuits, and memory in separate planar regions on the silicon die. LogicFolding eliminates this physical boundary by folding logic circuits vertically into a two-layer structure. Instead of spreading transistors flat, the architecture stacks them in the vertical dimension, drastically shortening internal wiring. This reduction in interconnect length lowers both resistance and capacitance, enabling faster signal propagation at lower power. The result is a chip that achieves higher transistor density and better performance without requiring a more advanced fabrication process.
Quantified Gains: 53.5% Density Increase, 41% Power Efficiency Boost
Huawei’s published numbers for the next-generation Kirin chip, slated for mass production in autumn 2026, are striking. Compared to a conventional SoC design on the same manufacturing node, the LogicFolding-based Kirin achieves a 53.5% increase in transistor density, reaching 238 MTr/mm². The performance-core power efficiency improves by 41%, and the maximum clock frequency rises 12.7% to 3.1 GHz. To put this in perspective, the current Kirin 9030 Pro has a transistor density of around 125 MTr/mm². A jump to 238 MTr/mm² represents nearly a doubling in density — all through design innovation alone, without moving to a smaller lithography node.
| Metric | Conventional SoC | LogicFolding Kirin |
|---|---|---|
| Transistor Density | ~125 MTr/mm² | 238 MTr/mm² (+53.5%) |
| P-Core Power Efficiency | Baseline | +41% |
| Max Clock Frequency | ~2.75 GHz | 3.1 GHz (+12.7%) |
Roadmap to 1.4nm Equivalent Density by 2031
Huawei has set a target of achieving 1.4nm equivalent transistor density by 2031 using the τ Scaling Law and LogicFolding. The word “equivalent” is crucial. Huawei is not claiming it will manufacture chips on a 1.4nm process — it cannot, because it lacks access to EUV tools. Rather, the company asserts that through design ingenuity and system-level optimisation, it can match the density that TSMC’s 1.4nm node (A14) will deliver. TSMC plans to begin volume production of its A14 process in 2028. Huawei’s 2031 target thus trails by three years — a remarkable achievement given that TSMC wields the world’s most advanced lithography equipment while Huawei operates under a US-imposed export ban that blocks it from even purchasing EUV machines.
The comparison underscores two fundamentally different trajectories. TSMC reaches 1.4nm through process leadership — smaller transistors, better materials, and EUV-based patterning. Huawei reaches a 1.4nm-equivalent density through design leadership — rearranging the same transistors more intelligently to pack more function into the same space. Both aim at a similar endpoint, but the path each takes could not be more different.
Six Years of Validation: 381 Chip Variants Already Produced
A key claim that lends credibility to Huawei’s announcement is the track record. He Tingbo revealed that over the past six years, Huawei has designed and fabricated 381 different chip types using the τ Scaling Law methodology. These chips cover a broad range of applications, from smartphone SoCs to AI accelerators, and have been successfully mass-produced. This is not a laboratory curiosity — it is a design philosophy that has already proven itself in volume manufacturing. The company has had to innovate because it had no choice. When the US sanctions began in 2019, Huawei was the world’s second-largest smartphone maker. Cut off from TSMC’s foundry services and barred from acquiring EUV equipment, the company redirected its focus from process scaling to design scaling. The τ Scaling Law is the fruit of that seven-year pivot.
Commercial Debut: Next-Generation Kirin Chip in Autumn 2026
The first commercial product to incorporate LogicFolding will be the next-generation Kirin chip, expected to debut in autumn 2026. Industry sources indicate the chip will power Huawei’s flagship Mate series smartphones, marking the first time the LogicFolding architecture appears in a shipping product. If the announced specifications hold up in independent testing, the chip will represent a watershed moment for the semiconductor industry. It will demonstrate that design innovation can partially compensate for manufacturing constraints, offering a potential blueprint for other companies facing similar equipment limitations.
Independent Verification Still Pending
For all the bold claims, several caveats deserve attention. First, the term “1.4nm equivalent” is inherently slippery. Modern process node names no longer correspond to any physical dimension; TSMC’s “1.4nm” is itself a marketing label denoting a generation of density and performance, not a literal gate length. Huawei is operating in the same ambiguous space, using “equivalent density” to position itself relative to the industry leader. Second, the numbers — 53.5% density improvement, 41% power efficiency gain, 12.7% clock uplift — are Huawei’s own published figures. No independent third party has verified them, and the company has not disclosed the baseline “conventional SoC design” against which these improvements are measured. How much of that baseline was already optimised for the τ approach? Without that context, the improvement percentages are difficult to assess.
Nonetheless, the decision to present the τ Scaling Law at a peer-reviewed venue like IEEE ISCAS and to submit a paper to SCIENCE CHINA Information Sciences signals that Huawei is serious about subjecting its ideas to academic scrutiny. The company’s leader has stated that “no single company can find all the answers in semiconductor evolution” — an implicit invitation for the broader industry to adopt the τ Scaling Law as a common framework. Whether the industry accepts that invitation remains to be seen, but the autumn 2026 Kirin chip will provide the first concrete, testable proof point. The answer is not far off.
