The relentless march toward ever-smaller, more powerful, and efficient semiconductors has entered a decisive new phase. IBM and Lam Research, two titans of semiconductor research and manufacturing technology, have announced a strategic partnership aimed squarely at validating the complete manufacturing processes needed to produce logic chips with features smaller than one nanometer. This collaboration, centered at IBM’s research facility in Albany, New York, represents a critical step in moving from theoretical breakthroughs to practical, manufacturable technology for the next decade of computing.<\/p>\n
Albany Nanotech, a world-class semiconductor research hub, will serve as the operational heart of this ambitious initiative. This facility is uniquely equipped with the advanced tools required for such frontier research, including the first High-Numerical Aperture (High-NA) Extreme Ultraviolet (EUV) lithography scanner in North America. The partnership will leverage this ecosystem to pioneer the integration of a key enabling technology: dry photoresist processes.<\/p>\n
Traditional photoresists, the light-sensitive materials used to pattern circuits, are applied in a liquid state. The “dry resist” process, which Lam Research specializes in, applies the resist material via a vapor deposition technique. This method offers superior uniformity and control at atomic scales, which becomes non-negotiable when patterning features that are merely a few atoms wide. Integrating this dry process with the unprecedented resolution of High-NA EUV is a foundational challenge the partnership must solve.<\/p>\n
Extreme Ultraviolet lithography, using light with a wavelength of 13.5 nanometers, is already the workhorse for producing today’s most advanced chips at the 3nm and 2nm nodes. High-NA EUV is the next evolutionary leap. By increasing the numerical aperture\u2014essentially widening the lens\u2014the technology improves resolution and shrinks the minimum printable feature size by roughly 30%. This leap in precision is what makes the sub-1nm realm physically attainable, allowing for denser, more complex circuit patterns that were previously impossible to manufacture.<\/p>\n
The agreement moves beyond component research to focus on validating full, integrated process flows. This holistic approach is crucial because at these scales, every step of fabrication interacts with every other. The partnership will concentrate on three interlocking technological pillars essential for sub-1nm logic.<\/p>\n
First is the continued evolution of transistor architecture. The industry is transitioning from FinFET transistors to Gate-All-Around (GAA) designs, specifically nanosheet transistors. In these structures, the silicon channel through which current flows is shaped like a thin, horizontal sheet surrounded by the gate on all four sides, enabling better electrostatic control. The next step, which IBM has pioneered, is the “nanosheet stack” or “nanostack,” which involves stacking these sheets vertically to increase drive current and performance without increasing the transistor’s footprint.<\/p>\n
Second, and equally revolutionary, is the implementation of backside power delivery. In all modern chips, the intricate web of wires that delivers electricity (the power delivery network) and the wires that carry data signals are intertwined on the front side of the silicon wafer. This creates a tangled mess of congestion and resistive power loss, a problem that worsens dramatically at smaller nodes. Backside power delivery flips this script by moving the entire power network to the back of the silicon wafer, freeing the front side exclusively for signal routing. This separation reduces voltage drop, improves energy efficiency, boosts performance, and simplifies the design process. IBM’s 2nm test chip in 2021 was a landmark demonstration of this technology.<\/p>\n
The monumental challenge is not just perfecting nanosheets or backside power in isolation, but integrating them into a cohesive, high-yield manufacturing flow. This is where the IBM-Lam partnership is targeted. Lam Research brings its deep expertise in deposition, etch, and cleaning processes\u2014the tools that physically build and shape the transistors and interconnects at an atomic level. IBM contributes its system-level design knowledge, integration prowess, and experience in novel materials science. Together, they will work to sequence hundreds of process steps so that building a nanostack transistor does not interfere with the precision required for backside power delivery, all while using the dry resist and High-NA EUV patterning.<\/p>\n
The path below 1nm is fraught with physical and engineering obstacles that this partnership must confront. Atomic-scale uniformity becomes paramount; a variation of a few atoms in a transistor channel can drastically alter its performance. New materials beyond silicon, such as germanium or 2D materials like transition metal dichalcogenides, may need to be introduced into the flow. Furthermore, managing heat dissipation in such incredibly dense structures is a growing concern. The dry resist process is one key to addressing the uniformity challenge, while the collaboration’s focus on full-flow validation is designed to identify and solve these integration headaches early in the development cycle.<\/p>\n
This partnership is a significant move in the global race for semiconductor supremacy. While foundries like TSMC, Samsung, and Intel are driving their own roadmaps to 2nm, 1.4nm (14A), and beyond, the IBM-Lam alliance operates at the pre-competitive research level. Their goal is to de-risk the most challenging aspects of the technology, creating a proven toolkit of processes and integration schemes that the entire industry can eventually adopt. This model has proven successful before; IBM’s early research on 7nm and 5nm technologies laid the groundwork for today’s production nodes. By proving the viability of the sub-1nm manufacturing blueprint, they aim to accelerate the entire ecosystem’s timeline.<\/p>\n
The implications extend far beyond faster smartphones. The computing efficiency gains promised by sub-1nm technology are critical for sustainable data centers, the feasibility of complex artificial intelligence models, next-generation networking, and advancements in quantum computing control systems. It represents the foundational infrastructure for the next wave of technological innovation.<\/p>\n
The work beginning in Albany is not about designing a single chip, but about proving that the most advanced chips imaginable can be built reliably, at scale. By validating the complete marriage of High-NA EUV lithography, dry resist processes, advanced transistor architectures, and backside power delivery, IBM and Lam Research are not just pushing the boundary of the possible\u2014they are methodically constructing the roadmap and the tools to make it a manufacturing reality. The outcome of this collaboration will define the practical limits of silicon for the coming generation, determining how much further Moore’s Law can be extended through engineering ingenuity and material science.<\/p>\n","protected":false},"excerpt":{"rendered":"
IBM and Lam Research collaborate to validate sub-1nm chip manufacturing using high-NA EUV lithography at Albany Nanotech.<\/p>\n","protected":false},"author":7,"featured_media":92022,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"fifu_image_url":"https:\/\/cards.overcentral.com\/cards\/en\/18769.png","fifu_image_alt":"IBM and Lam Research Partnership Validates Sub-1nm Logic Process Flows with High-NA","footnotes":""},"categories":[31],"tags":[],"class_list":["post-18769","post","type-post","status-publish","format-standard","has-post-thumbnail","category-technology"],"fifu_image_url":"https:\/\/cards.overcentral.com\/cards\/en\/18769.png","fifu_image_alt":"IBM and Lam Research Partnership Validates Sub-1nm Logic Process Flows with High-NA","fifu_redirection_url":"https:\/\/www.ainvest.com\/news\/lam-research-forms-partnership-jsr-advance-high-na-euv-lithography-2509\/","_links":{"self":[{"href":"https:\/\/overcentral.com\/en\/wp-json\/wp\/v2\/posts\/18769","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/overcentral.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/overcentral.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/overcentral.com\/en\/wp-json\/wp\/v2\/users\/7"}],"replies":[{"embeddable":true,"href":"https:\/\/overcentral.com\/en\/wp-json\/wp\/v2\/comments?post=18769"}],"version-history":[{"count":0,"href":"https:\/\/overcentral.com\/en\/wp-json\/wp\/v2\/posts\/18769\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/overcentral.com\/en\/wp-json\/wp\/v2\/media\/92022"}],"wp:attachment":[{"href":"https:\/\/overcentral.com\/en\/wp-json\/wp\/v2\/media?parent=18769"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/overcentral.com\/en\/wp-json\/wp\/v2\/categories?post=18769"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/overcentral.com\/en\/wp-json\/wp\/v2\/tags?post=18769"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}