For nearly a decade, the hardware race underpinning the artificial intelligence revolution has unfolded with remarkable speed, producing a bewildering array of specialized chips, cards, and systems. Understanding which technologies actually deliver on their promises has become a critical task for national security, industrial competitiveness, and scientific research. Since 2018, a team at the Massachusetts Institute of Technology’s Lincoln Laboratory Supercomputing Center<\/a> (LLSC) has been systematically cataloging this landscape through the Lincoln AI Computing Survey (LAICS, pronounced “lace”), now spanning six published papers and coverage of more than 120 distinct commercial AI accelerators. The survey provides an independent, data-driven map of a field where marketing claims often outpace measurable reality, and where the difference between a well-chosen accelerator and a poor one can mean millions of dollars and years of development time.<\/p>\n The survey was born from direct demand. Around eight years ago, the number of research papers describing novel AI accelerators and commercial product announcements began to surge. Government sponsors of Lincoln Laboratory’s work started asking pointed questions about which technologies were viable, which were hyped, and which merited investment. “That was motivation enough to start the survey,” says Albert Reuther, a staff member at the LLSC, which operates and optimizes high-performance computing systems used by thousands of laboratory research staff. What began as an internal effort to answer those questions has grown into one of the most comprehensive publicly available assessments of the AI<\/a> accelerator market.<\/p>\n At its core, LAICS is a comparative analysis built on two primary metrics: peak performance and peak power consumption. The team then organizes accelerators by form factor, distinguishing between individual chips, cards (which include supporting circuitry and memory), and complete systems. All data is drawn from publicly available sources, a constraint that introduces its own challenges, as many companies prefer to keep detailed performance and power figures confidential. Despite this limitation, the survey has expanded substantially. The first paper in the series examined 57 accelerators; the most recent installment covers more than 120, reflecting both the proliferation of new entrants and the team’s refined methodology for extracting comparable data from scattered public disclosures.<\/p>\n Reuther runs daily news and citation searches that flag new technical press articles, company announcements, and industry presentations to keep the survey current. This vigilance has revealed a persistent pattern: every year, five to ten new startups receive funding, announce their products, and release new AI accelerators. “One might think that the landscape is saturated enough, but then another batch of innovative accelerators is introduced,” Reuther notes. The pace shows no sign of slackening. In just the past few months, six new startups have announced their first AI accelerators, ensuring that the LAICS team will have fresh material for future editions.<\/p>\n AI accelerator technology encompasses several fundamentally different architectures, each with distinct strengths and limitations. Central processing units (CPUs) remain the workhorses of general-purpose computing, capable of handling a wide range of tasks but offering relatively low efficiency for the massively parallel workloads characteristic of neural networks. Graphics processing units (GPUs), originally designed for rendering images, have become the dominant platform for deep learning due to their large number of cores and ability to perform many calculations simultaneously. Application-specific integrated circuits (ASICs) are purpose-built for particular algorithms, offering the highest efficiency for those specific tasks but zero flexibility beyond their original design scope. Field-programmable gate arrays (FPGAs) and dataflow accelerators occupy a middle ground, providing reconfigurability that allows them to be adapted to different workloads, though often with trade-offs in peak performance or ease of programming.<\/p>\n The LAICS team does not simply rank these architectures against one another. Instead, the survey illuminates which designs are best suited to which applications. Efficiency and performance vary widely depending on how an accelerator is designed, the numerical precision it supports, the memory bandwidth available, and the interconnection topology between processing elements. By comparing these characteristics systematically, the survey enables informed decisions rather than blanket endorsements of one architecture over another.<\/p>\n While each LAICS paper provides a snapshot of the current market, the series as a whole reveals deeper trends. The 2022 paper investigated the sources of performance increases observed over previous years. The analysis identified two primary drivers: smaller, denser transistor designs that pack more computational units onto a single chip, and the adoption of lower numerical precision. Calculating with fewer significant digits, a technique known as reduced-precision arithmetic, speeds up operations and reduces memory requirements without unacceptable loss of accuracy for many AI workloads. Together, these advances have enabled dramatic year-over-year improvements in performance per watt, though the rate of improvement shows signs of slowing as transistor scaling approaches fundamental physical limits.<\/p>\n The latest paper in the series shifted focus to architectural choices, examining how different design decisions affect system-level performance. The team analyzed the impact of adding more cores per processor, increasing parallel performance through wider data paths, and integrating larger on-chip memories. These architectural variations produce markedly different performance profiles, and the survey provides a framework for matching those profiles to specific application requirements. A model optimized for real-time inference on edge devices, for example, has little in common with a training system designed for large-scale data centers.<\/p>\nWhat LAICS Measures and Why It Matters<\/h2>\n
The Architecture Landscape: CPUs, GPUs, ASICs, FPGAs, and Dataflow Accelerators<\/h2>\n
Key Findings Across Six Papers<\/h2>\n